Coordinate generation system

ABSTRACT

A coordinate generation system providing deflection signals for the X and the Y coordinates of an oscilloscope type display for producing a line on the display having a direction synchronized with a source of direction. Such a source of direction is typically a radar antenna in which case the line produced on the display is directed in the direction of the antenna such as in a plan position indicator (PPI). The coordinate generation system utilizes a sequence of pulses, each of which indicates a predetermined incremental change in the direction of the source of direction, for addressing a memory which stores corresponding incremental changes in the magnitude of the deflection signals to be applied to the X and to the Y coordinates of the display. The stored increments are accumulated and converted to analog signals suitable for driving the X and the Y coordinate axes of the display.

United States Patent [191 Christopher Feb. 26, 1974 COORDINATEGENERATION SYSTEM [57] ABSTRACT [75] Inventor: Daryl J; Christopher,Framingham,

Mass.

[73} Assigncez Raytheon Company, Lexington, A coordinate generationsystem providing deflection Mass signals for the X and the Y coordinatesof an oscilloscope type display for producing a line on the displayFiledi June 1 1 having a direction synchronized with a source of di-[21] APP] NO; 265,121 rection. Such a source of direction is typically aradar antenna in which case the line produced on the display is directedin the direction of the antenna such as U.S. DP, in a plan positionindicator The coordinate gen- Int. Cleration ystem utilizes a equence ofpulses each of Field of Search 343/5 5 DP, 5 EM which indicates apredetermined incremental change in the direction of the source ofdirection, for address- References Cited ing a memory which storescorresponding incremental UNlTED STATES PATENTS changes in the magnitudeof the deflection signals to 3,178,709 4/1965 White et a]. 343/ 5 R x beapplied to the X and to the Y coordinates of the 3 2 09 7 9 Swa]e et aL343 5 p X display. The stored increments are accumulated and 3,292,03412/1966 Braaten 343/5 DP X converted to analog signals suitable fordriving the X 3,343,159 9/1967 Van Breugel 343/5 R and the Y coordinateaxes of the display.

Primary ExaminerT. H. Tubbesing Attorney, Agent, or FirmJoseph D.Pannone; David M. Warren; Milton D. Bartlett 24 Claims, 8 DrawingFigures lmummN GENERATOR /1 3. 58A 60 4 l INQR MENT STORAGE svs 56AANALOG I 1 n 1 JfifL IS'NU INVERT I I ADDRESS MEMORY I SINE ANALOG (SINEACCUM MULT SWITCH COUNTER F INCR) D/A 1 90A I I INCR/DECR |RE5ET F!RESET 3,19A l DETECTOR S1GN(POS/NEG)BIT x LA. E H s. 1 9/ l SIG CLOCK-s|o JNVCKEMEINT STORAGE svs 54B 555 T i }62/% i i i laonxNrl I vADDRESS MEMORY cos|NE ANALOG I C E ACCUM MULT YDISPLAY COUNTER mm T L [MSWITCH I Z I a 905 I I a 645 l I 25 INCR/DECR IRESE 66E l RESET 1 l T IDEiECTOR SIGN BIT LL J Z l l a .I SIG T T T TEABECIiR/E? L i F" i jiMlNG RANGE 24 I 1 J. E 32 1 68 70 1 N TRANSMITTING 72 ANTENNA aRECEIVING CIRCUITRY PATENTEDFEBZBIBM I $794,993

SHEEI 1 0F 5 FUNCTION I I SSENERATOR INCREIvIENT STORAGE SYSTEM 94 lCLOCK-+9 ADDRESS MEMORY RESETJ COUNTER DIGITAL ACCUMULATOR T T I NCR [COT OL I I I I 54 I F/G 3 1 66 RESET INCR I II 6am IGN i CONTROL DETECTORINCREIvIENT STORAGE SYSTEM /96 M 7 80 EMORY I IiI C R EII/IENT ACCUM J9CLO B SECTION 1 UP/DN) f INE -GATE+ADDRESS A RESET I UP/ DOWN .1;COUNTER COUNTER Mg; SWITCH /IL//2 SECTION I A I. 82 I I B I COS I INCRE-INHIBIT UP/ DOWN MENT l- I 98 RESET CONTROL I SWITCH CONTROL COUNTEROETECTOR 7 III ACCUM UP/DN I 605 COUNTER INCR/DECR & RESET CONTROLS:SIGN BITS F/G 4 v. 0

COORDINATE GENERATION SYSTEM GOVERNMENT CONTRACT The invention hereindescribed was made in the course of or under a contract or subcontractthereunder, (or grant) with the Department of Defense.

BACKGROUND OF THE INVENTION In the past, both analog and digital systemshave been utilized in radar systems for developing deflection signalsfor the X and the Y coordinates of a display and for synchronizing thesedeflection signals with the position of a rotating antenna. Where highaccuracies are required in the generation of these deflection signals,the use of ganged course and fine resolvers becomes cumbersome in theanalog systems of the prior art. Accordingly, it has become the practicein modern systems to utilize digital techniques in which multipleterminal encoders, mechanically coupled to the rotating antenna,transmit multiple bit angle data for each increment of antenna rotation.Or, alternatively, the prior art digital systems may utilize an encodertransmitting only a sequence of clock pulses synchronized to the antennarotation with each clock pulse representing an increment in antennarotation, these clock pulses being utilized to drive circuitry whichoperates with multiple bit signals for the providing of multiple bitdeflection signals. A problem arises in the digital systems of the priorart in that a substantial amount of digital equipment is required toprocess the multiple bit signals since many bits are required in highlyaccurate systems.

SUMMARY OF THE INVENTION The preceding problem of prior art systems isovercome with a coordinate generation system in accordance with theinvention which utilizes a sequence of pulses synchronized to a sourceof direction, such as a radar antenna, for addressing a memory whichstores incremental changes in display coordinate signals. In a preferredembodiment of the invention, these incremental signals are simply theleast significant bit of multiple bit sine and cosine signals utilizedin the driving of the X and the Y coordinates of a fixed displaydeflection system. The angular increments represented by each of thepulses in the sequence of pulses from the source of direction issufficiently small such that the value of the sine and the value of thecosine never changes by more than one least significant bit for eachincrement in the change of direction. An accumulator is provided forcombining these increments into a multiple bit digital number which isthen converted to an analog signal suitable for driving a deflectionaxis of the display. The memory may store increments of the sine and thecosine waveform or, alternatively, the sine and the cosine functions maybe modified to compensate for any nonlinearities in the displaydeflection system. And, if desired, the stored function increments maybe selected so as to provide deflection signals resulting in a curvedtrace rather than a straight line, as may be useful, for example, inproducing a symbol on the display.

Alternative embodiments for implementing the incremental storage featureare disclosed.

invention are explained in the following description taken in connectionwith the accompanying drawings wherein:

FIG. 1 shows a boat equipped with a radar system incorporating thecoordinate generation system of the invention for providing a planposition indicator (PPI) display synchronized with the direction of aradar beam emanating from the antenna;

FIG. 2 is a block diagram of the coordinate generation system utilizedin FIG. 1;

FIG. 3 is a block diagram of an alternative embodiment of an incrementstorage system utilized in the coordinate generation system of FIG. 2;

FIG 4 is a block diagram of a second alternative embodiment of theincrement storage system of FIG. 2;

FIGS. 5 and 6 are, respectively, a table of incremental values of thesine and cosine functions and a schematic representation of theincrement storage system of FIG. 4 which are useful in explaining theincrement storage system of FIG. 4;

FIG. 7 is a block diagram showing the use of the coordinate generationsystem of FIG. 2 in providing symbols on a cathoderay tube type displayhaving a fixed deflection yoke for deflecting the electron beam in X andY directions; and

FIG. 8 is a block diagram of an alternative embodiment of the inventionadapted for providing a sequence of traces having the form of a symbol.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, thereis seen a pictorial representation of the coordinate generation system20 of the invention mounted on a boat 22 and utilized in a radar systemcomprising an antenna 24 emitting a beam 26 of radiation, 21 display 28shown in dashed lines within the boat 22, a transceiver 30interconnecting the antenna 24 and the display 28 via lines 32 and 34, afunction generator 36 coupled to the display 28 via lines 38A-B, and anencoder 40 mechanically connected to a drive unit 42 of the antenna 24and coupled via line 44 to the function generator 36. The coordinategeneration system 20 may equally well be utilized in a sonar system (notshown) in which case the antenna 24 would be a sonic radiator displosedwithin the ocean 46. As the boat 22 sails through the ocean 46, theradar antenna 24 is rotated by the drive unit 42 so that the beam 26scans azimuthally the region around the boat 22. The transceiver 30 isof a well-known form utilized in radar systems for providing a signal tobe transmitted via the antenna 24 and for receiving signals reflectedfrom distant objects along the direction of the beam 26 to the antenna24. The transceiver 30 provides signals along line 34 for indicating onthe display 28 the presence of nearby objects. The encoder 40 transmitsa succession of clock pulses along line 44 to the function generator 36,the repetition frequency of these clock pulses being synchronized withthe rate of rotation of the antenna 24 and its drive unit 42 so thateach of these clock pulses represents a specific increment in the angleof rotation of the antenna 24 about its axis. The function generator 36,in accordance with the invention, utilizes these clock pulses on lone 44as well as a reset pulse also provided on line 44 to generate X and Ydeflection signals on lines 38A-B for providing the well-known radialtrace of a PPI for the display 28.

Referring now to FIG. 2, there is seen a detail block diagram of thecoordinate generation system showing the function generator 36, theencoder 40, mechanically connected via dashed line 48 to the drive unit42 and the antenna 24, the display 28 and the transceiver 30, all ofwhich have been seen previously in FIG. 1. The function generator 36 isseen comprising two increment storage systems SOA-B each of which iscoupled by a register 52 to the line 44 and the encoder 40, twoaccumulators 54A-B, two digital-to-analog converters 56A-B, two analoginverting amplifiers SSA-B and two analog switches 60AB. The suffixes Aand B are appended to identify respectively the components utilized ingenerating the X and Y deflection signals. Thus, the incremental storagesystem 50A, the accumulator 54A, the digital-to-analog converter 56A,the analog inverting amplifier 58A and the analog switch 60A areutilized in generating the X deflection signal on line 38A while thecorresponding ones of these components labeled with the letter B areutilized for generating the Y deflection signal on line 38B. Theincrement storage systems 50AB are seen comprising respectively addresscounters 62AB, memories 64A-B which in the preferred embodiment have theform of read-only memories, and detectors 66A-B of binary numbers. Thetransceiver is seen comprising a timing unit 68, a ranging unit 70 andcircuitry 72 transmitting and receiving signals via the antenna 24.

The line 44 from the encoder is depicted in FIG. 2 as being a cablehaving internal electrical conductors for transmitting clock pulsesignals and a reset signal, these conductors being representeddiagrammatically in the figure by lines 74 and 76 respectively for theclock and reset signals. The clock and reset signals pass through theregister 52 in accordance with timing signals on line 78 from the timingunit 68 and appear respectively on lines 80 and 82. The purpose of theregister 52 is to temporarily store the clock and reset signals duringthe relatively short time interval in which a line is constructed uponthe face of the display 28, it being readily apparent that if anadditional clock signal arrives at the increment storage systems A and Bwhile such a line is being constructed on the face of the display 28,the remaining portion of the line would be redirected so that anundesirable bend would appear in the line. Accordingly, the timing unit68 permits the clock and reset signals to be read out of the register 52only during the intervals between the construction of the traces on thedisplay 28. Alternatively, the register 52 may be deleted if the timingunit 68 and the antenna drive unit 42 are synchronized such as byproviding synchronizing pulses (not shown) from the drive unit 42 to thetiming unit 68, such a synchronization insuring that no clock or resetsignal would appear on lines 74 and 76 during the writing of a trace onthe display 28, but rather that one clock pulse would appear betweeneach trace to update the direction of the next trace.

The increment storage systems 50A-B operate as follows. A reset signalon line 82 is applied to each address counter 62A-B to set it to apredetermined binary number. Assuming that a reset signal is transmittedonce per revolution of the antenna 24, for example, whenever the antennaazimuth angle is zero relative to the central line of the boat 22 ofFIG. 1, both address counters 62A-B are set to zero, and the detectors66A-B, upon detecting the number zero, transmit reset signals to theaccumulators 54A-B to reset the accumulator 54A to the value of zerowhile resetting the accumulator 54B at a maximum value, a maximum valueof 1023 being utilized in the preferred embodiment of the invention. Themaximum value in the accumulator 54B is unity, corresponding to thecosine of degrees, and is applied via the line 90B to thedigital-to-analog converter 56B which converts this binary number to amaximum deflection voltage for the Y axis of the display 28, while thevalue of zero to which the accumulator 54A has been reset is tranmittedvia the line 90A to the digital-toanalog converter 56A to provide a zerodeflection on the X axis of the display with the resultant trace beingvertically directed to show that the antenna 24 is facing the bow of theboat 22. The lines 90A-B are drawn as heavy lines to indicate thetransmission of multibit numbers. It is understood that the diagram ofFIG. 2 relates to a ships heading oriented display, and that a northoriented display could be constructed by utilizing a well-known form ofcoordinate converter (not shown) coupled to a gyrocompass (not shown).

Referring now specifically to the operation of the components whichprovide the X signal on line 38A, it is noted that, upon the resettingof the address counter 62A to zero, the data in the memory slot of thememory 64A at the zero address is made available to the accumulator 54A.When the next clock signal arrives on line 80, the address counter 62Acounts a count of one and addresses the memory 64A to make available tothe accumulator 54A such data as is stored in the number one bin of thememory 64A. And, similarly, upon appearances of successive clock pulseson line 80, the address counter 62A advances to successively highercounts and addresses the memory 64A to tranmit data from thecorresponding bins to the accumulator 54A. The sine memory 64A storesinformation with respect to the value of a sine wave relative to anangle corresponding to the digital number of the address counter 62A.Since the memory 64A stores only the least significant bit of each valueof the sinusoid function, each memory bin has a capacity of only onebit, there being in the preferred embodiment 2048 bins of memory and theaddress counter 62A counts from zero to 2047 inclusive. The encoder 40transmits 2048 clock pulse signals on line 74 for each quadrant or 90rotation of the antenna 24 for a total of 8192 pulses per revolution ofthe antenna 24. As has already been noted, the accumulator 54Aaccumulates a maximum count of 1023 which is a 10-bit binary number.This is only one-half the total number of memory bins provided by thememory 64, the reason being that the increments in antenna angularposition must be sufficiently small such that successive values of thesinusoid provided by the memory 64A must not differ in size by more thanone LSB (least significant bit). It has been found that by transmitting2048 I 1 bits) clock signals per quadrant, a 10- bit accuracy can beprovided in the deflection signals without having the value of thesinusoid increased by more than one LSB, it is only necessary to storein the memory 64A the LSB portion of each value of the sinusoid. Similarcomments apply to the address counter 62B and the cosine memory 648.

As is well known, the value of the sinusoid proceeds from zero to unityduring the first quadrant and then reverts to zero in the secondquadrant, this procedure being repeated during the third and fourthquadrants. Since the same values of the sinusoid appear repetitivelyduring each revolution of the antenna 24, it is only necessary to storethe set of values appearing during one quadrant of the revolution of theantenna 24. In the event that it is desired to correct nonlinearities inthe deflection system of the display 28, then the data stored within thememory 64A must be altered slightly to correct for the nonlinearity, thealteration in the data differing from one quadrant to the next. Undersuch circumstances, it is necessary to store within the memory 64Asufficient data for an entire revolution of the antenna 24, this beingin the case of the preferred embodiment of the invention, 8192 storagebins each of which stores'one LSB. For ease of explaining the invention,the diagram of FIG. 2 is drawn for the case where data for all fourquadrants is stored within the memory 64A; a system wherein a memorystores only the data of one quadrant will be described hereinafter withreference to FIG. 4.

Since the value of the sine appearing on the line 90A increases anddecreases periodically during each revolution of the antenna 24, theaccumulator 54A must be made to increment its value with each bitreceived from the memory 64A during one quadrant and to decrement itsvalue with each bit received from the memory 64A during the nextquadrant of revolution of the antenna 24. The detector 66A provides anincrement /decrement signal for the accumulator 54A in response to themost significant bit and the second most significant bit of the binarynumber provided by the address counter 62A. Thus, during the interval oftime when the numbers of the address counter 62A run from zero through2047, the detector 66A commands the accumulator 54A to increment itsvalue, while during the interval of time when the numbers 2048 through4095 appear at the address counter 62A, the detector 66A commands theaccumulator 54A to decrement its count. The increment command is againprovided by the detector 66A when the address counter 62A shows a countof 4096 and a decrement command when the count reaches 6144. Since thesinusoid alters its sign from positive to negative as the antenna 24passes the 180 point, while the accumulator 54A only provides positivevalues or the absolute value of the sine on the line 90A, the detector66A provides a sign bit indicating a positive or negative value of thesinusoid, the positive sine being indicated by the detector 66A when thecount of the address counter 62A has a value of from zero to 4095 andthe negative value when the address counter shows a count of from 4096to 8191. The analog signal provided by the digital-to-analog converter56A is applied via the inverting amplifier 58A to the switch 60A as wellas directly to the switch 60A so that the output of the switch on line38A may be either the inverted (negative) value of the sinusoid or thedirect (positive) value of the sinusoid.

Similar commments apply to the operation of the components providing theY signal on line 388 except for a slight difference in operation,namely, that the detector 66B applies a decrement signal to theaccumulator 54B when the number zero appears in the address counter 62Band applies an increment signal when the number 2048 appears in theaddress counter 62B, these commands being repeated during successivequadrants of the antenna rotation. A sign bit indicating a positivevalue of the cosine is provided by the detector 66B when the addresscounter 62B shows a count of 6144 and a negative value of the cosinewhen the address counter 628 shows a count of 2048. This sign bit isapplied to the analog switch 608 for selecting the inverted output ofthe amplifier 58B or the direct output of the cosine digital-to-analogconverter 56B in the same manner as was described above with referenceto the analog switch 60A and the analog inverting amplifier 58A.

Each digital-to-analog converter 56A-B is provided with a multiplyingcapability for multiplying the values of the sinusoids on lines 90A-B bythe output signal on line 91 of the ranging unit 70, this output signalbeing a sweep waveform which serves to scale the value of the sinefunction applied to the digital-to-analog converter 56A and the cosinefunction applied to the digital-to-analog converter 568 with the resultthat two ramp waveforms appear at the X and Y defection signals on lines38A and 38B. These two ramp deflection signals provide a linear trace onthe display 28 having a horizontal component proportional to the Xsignal on line 38A and a vertical component proportional to the Y signalon line 38B. Upon successive updatings of the addresses provided by theaddress counters 62, the relative magnitudes of the X and Y rampdeflection sig nals on the lines 38A and 38B varies so that successivetraces on the display 28 are seen to pivot about the center of thedisplay in the manner of a PPl.

It is interesting to note with respect to the two ramp waveformsappearing on the lines 38A-B, that if a constant voltage were applied tothe reference input of each analog-to-digital converter 56A-B on line 91in lieu of the sweep waveform, then the X and Y deflection signals onlines 38A-B would correspond to the coordinates of a circular trace orarc on the display 28, with the end of the arc corresponding to theorientation of the antenna 24, these X-Y deflection signals are ideallysuited for driving a resolver (not shown) or similar typeelectromechanical system wherein it is desired to orient a mechanicaldevice in accordance with a prescribed direction. This interconnectionwith the resolver is implemented by connecting the signals on lines38A-B to the X and Y (or north and south) terminals of the resolverwhile applying a (preferably) constant voltage on the line 91.

As was mentioned before, if a clock signal on line 80 were applied tothe address counters 62A-B during the interval of time in which a traceis being produced on the display 28, the relative amplitudes of the Xand Y deflection signals would vary providing a bend in the trace;however, the range sweep provided by the ranging unit is synchronizedvia the timing unit 68 to the register 52 and, accordingly, the rangesweep may be performed slowly or rapidly for displaying respectively along range or a short range while being free of the appearance of anyclock signals on line 80. It is apparent that if a long range isdisplayed, a number of clock signals will be temporarily stored in theregister 52 during each of the long-range range sweeps with the resultthat successive traces on the display 28 will be more further spacedapart in azimuth angle. The timing unit 68 also synchronizes theoperation of the circuitry 72 with that of the ranging unit 70 so thattarget returns appear on the Z axis signal on line 34 during successivegenerations of the range sweep by the ranging unit 70 in' a manner wellknown to radar systems.

It is also interesting to note that while the function generator 36 hasbeen depicted as having two channels for providing the X and the Ycoordinate signals, an additional channel (not shown) similarlycomprising an increment storage system, accumulator, digital-toanalogconverter with multiplying capability, inverting amplifier and switchmay similarly be connected to a register such as the register 52 and asource of scaling voltage such as the ranging unit 70 in a multiaxisdisplay in which it is desired to position a writing stylus or otherindicating means in three dimensions.

Referring now to FIG. 3, there is shown a block diagram of an incrementstorage system 92 which is an alternative embodiment to the incrementstorage system 50A or 50B previously described with reference to FIG. 2.The legends A and B are dropped here since FIG. 3 is equally applicablefor the X and the Y deflection signals. In FIG. 3 there are seen theaddress counter 62, the detector 66 and the accumulator 54 previouslyseen in FIG. 2. A memory 94 is provided for storing increments of thefunction (such as the sinusoid) to be applied to the deflection systemof the display 28 as was done by the memory 64 of FIG. 2, however, thememory 94 furthermore comprises additional storage space for each memoryand for storing a multiple bit number which serves as the control signalwhich is then detected by the detector 66. Recalling the oper ation ofthe increment storage system 50A of FIG. 2, the detector 66A receivedthe most significant bits of the address counter 62A and provided outputcontrol signals in response to the particular quadrant indicated bythese most significant bits. By way of contrast, in the embodiment ofFIG. 3, the binary number represented by the most significant bits isplaced in storage in the same bin as is stored the correspondingfunction increment. Thus, when the address counter 62 addresses aspecific bin within the memory 94, the detector 66 senses the multibitnumber which indicates which control signal is to be applied to theaccumulator 54 and the analog switch seen at FIG. 2. The implementationof FIG. 3 is useful when a nonsinusoidal function is to be applied tothe deflection system of the display 28. The memory 94 may be a corememory, a read-only memory or disc or a tape memory. A further advantageof the memory 94 is that the detector 66 may be eliminated by connectingthe reset terminal of the accumulator 54 directly to a control bit ofthe memory 94, and similarly connecting the increment/decrement controland the sine bit control to respective control bits of the memory 94.

It is also interesting to note that in the event that a non-sinusoidalfunction, such as some arbitrary wavy line function, is to be generatedby using the increment storage system 92 and the accumulator 54, theincrement/decrement control may be utilized on numerous occasions toincrement and decrement the accumulator 54 to provide for a wavy linetype function useful for character generation as will be described withreference to FIG. 7.

Referring now to FIG. 4, there is seen a block diagram of an incrementstorage system 96 which is an alternative embodiment to the incrementstorage system 50A of FIG. 2. The increment storage system 96 comprisesa counter 98, an address counter 100, a detector 102, a dual sectionmemory 104 having a section A and a sectin B which are simultaneouslyaddressed by the address counter 100 along line 106, and a switch 108.The switch 108 and the detector 102 apply signals to the accumulators54A-B, previously seen in FIG. 2. Since the sine and cosine incrementsare one-bit numbers, each accumulator 54A-B may comprise simply anup/down counter as is indicated in FIG. 4. The clock and reset signalspresented on lines and 82 of FIG. 2 are also provided in FIG. 4.

The operation of the increment storage system 96 provides for a savingin memory storage, this storage being implemented by the single memory104 having a total number of storage bins equal to that of the memory64A, with half the storage bins being provided in section A and theother half in section B of the memory 104. Increment signals aresimultaneouly provided by both section A and section B to the switch 108and these increment signals appear simultaneously on lines 110 and 112for applying these signals to the accumulators 54A-B.

The operation of the increment storage system 96 may be more readilyunderstood by referring to FIGS. 5 and 6 which show respectively a tableof sine and cosine data including incremental changes between successivevalues of the sine and the cosine, and a simplified model of the memory104 seen having stored increments corresponding to the values of thetable in FIG. 5. The switch 108 is also seen in pictorial form in FIG. 6where it is shown as a double-pole, doublethrow toggle switch todemonstrate its operation, the switch 108 actually comprising anelectronic switching circuit responsive to a switch control signal fromthe detector 102 of FIG. 4.

The tabulated data of FIG. 5 is shown with the numerals of the decimalsystem rather than in binary notation to simplify explanation of thefigures. The first column on the left shows nine angles corresponding toeight increments in angle of rotation of the antenna 24 of FIG. 1, therebeing eight increments of l l.25 between each of the angles. The secondand third columns show numerical values of the sine and the cosinerounded off to two decimal places. The third column shows increments inthe value of the sine between successive entries of the sine in column 2and, similarly, column 4 shows a decrement between successive values ofthe cosine presented in column 3. While it is understood that theembodiments of the invention presented in FIGS. 2, 3 and 4 utilize verysmall increments in the rotation angle of the antenna 24 such that theincrement in the values of the sine and the cosine never exceeds oneLSB, the tabulated data of FIG. 5 shows large increments in angle tomore readily present symmetrical properties of the sine and the cosineas well as the sine increment and the cosine decrement. In this respectit is noted that the order of the numerals appearing in the third columnfor the cosine function is the reverse of the order of the numeralsappearing in the second column for the sine function. And similarly, theorder of the numerals representing the cosine decrements in the fifthcolumn is reverse to the order of the numerals representing the sineincrements in the fourth column.

The numerals of the sine increment in the fourth column are presented inFIG. 6 such that the first four increments are presented in section Awhile the last four increments are presented in reverse order in sectionB thus giving the appearance of a folded memory with the fold takingplace immediately after the increment corresponding to the angle of 45.The line 106 of FIG. 4 is portrayed in FIG. 6 as four lines labeled A,B, C, and D, each of which represents a separate addressing of a pair ofstorage bins, one bin of each pair being in section A while the otherbin of that pair is in section B. The address corresponding to theletter A provides the increment 19 from section A and the increment 02from section B for the switch 108. With the switch 108 in position No.l, the increment from section B passes on to the cosine increment (ordecrement depending on whether the accumulator 54B of FIG. 4 isincrementing or decrementing) on line 112 while the increment of sectionA is passed via switch 108 on to line 110 to appear as a sine increment.In response to four successive clock signals on the line 80 in FIG. 4,the ad dress counter 100 of FIG. 4 advances through addressescorresponding to the letters A, B, C and D thereby transmitting via theswitch 108 four successive sine increments from section A to theaccumulator 54A and, simultaneously therewith, four successiveincrements from the section B to the accumulator 548.

After the address counter 100 has successively addressed simultaneouslyeach bin of section A and section B, the address counter 100 remainsmomentarily at the address of the last bin for the duration of one clocksignal interval and then counts down. This sequence of addressing may beseen in the next to the last column in which the address D is repeatedtwice. Similarly, when the address counter 100 has counted down to theaddress A the address A is also repeated a second time before theaddress counter 100 counts back up. The repetition of the addressing ofthe storage bins at both end of the memory 104 is accomplished by meansof a gate 114 in FIG. 4 through which the clock signals on line 80 passto the address counter 100. When it is desired to repeat an address suchas the address D or the address A of FIGS. and 6, the detector 102 sendsan inhibit signal to the gate 114 which blocks the passage of the nextclock pulse signal on line 80 so that the address counter 100 does notchange its count. The positions of the switch 108 for each of theaddressings of the memory 104 are presented in the last column whereinit can be seen that the address counter 100 counts up from A through Dwhile the switch 108 is in position No. l, and the switch 108 is inposition No. 2

when the address counter 100 counts down from D to,

Again referring to FIG. 4, the detector 102 senses the count of thecounter 98 and in response thereto provides the reset and the up/downcontrol for the address counter 100 as well as the aforementionedinhibit signal to the gate 114 and the switch control to the switch 108.The providing of the sine bits, the increment- /decrement control andthe reset controls by the detector 102 is accomplished in the manneranalogous to that described earlier with reference to the detector 66 ofFIG. 2. The counter 98 counts modulo a number proportional to onerevolution of the antenna 24 of FIG. 1, and as has been noted earlierwith reference to the preferred embodiment of the invention, a lO-bitaccuracy in the deflection signals of the display 24 of FIG. 2 requiredan 1 l-bit count per quadrant in which case the counter 98 counts modulo8192. The reset signal on line 82 ensures that the counter 98 presents acount of zero when the antenna 24 is oriented at an angle of 0 relativeto the center line of the boat 22. The detector 102 resets the addresscounter 100 to a value of zero at the beginning of each quadrant.

Referring now to FIG. 7 there is shown an alternative embodiment of theinvention wherein a pair of function generators 36, one such functiongenerator having been described in FIG. 2, are utilized in providing Xand Y signals to the deflection system of a display 116 for generatingcharacters upon the face 118 of the display 116. The clock, reset andscaling signals for each function generator 36 as well as the Z axissignal for the display 116 are provided by a programmer 120. Theoperation of the programmer 120 is readily apparent from the operationof the system 20 as described with reference to FIG. 2. Thus, the clockand reset signals are provided periodically for addressing increments ofthe character generation function stored within the memory of thefunction generator 36 as well as resetting the address counter of thefunction generator 36 to zero. The scaling signal as provided by theprogrammer 120 controls the radial distance of each point on the traceof the character being generated on the face of the display 116. One ofthe function generators 36 is utilized in positioning the character onthe face 118 while the second function generator 36 is utilized intracing the actual outline of the character on the face 118. The Xsignals from each of the two function generators 36 are summed togetherat a deflection amplifier 122A and the corresponding Y signals aresummed together at the deflection amplifier 122B so that the totalsignal applied to the deflection system of the display 116 representsthe contribution of the function generator 36 providing the position ofthe character as well as the contribution of the other functiongenerator 36 providing the trace of the character on the face 118. Inorder to provide a smooth curve to the characters being presented on theface 118 as the successive clock signals address successive bins in thememories of these function generators 36, two low pass filters 124A-B,each having a bandwidth equal, approximately, to the reciprocal of theclock signal repetition frequency, are provided for smoothing thetransitions in the analog voltages of the X and Y signals, thesetransitions occurring whenever a new increment is applied to theaccumulator of a function generator 36. The output signals of the lowpass filters 124A-B are applied to the X and Y axes of deflection yoke126 for deflecting the beam of a cathode-ray tube (represented by theface 118) for generating the trace of the face 118. An intensity controlcircuit 128 is provided for controlling the intensity of the traceappearing on the face 118 in response to the Z signal. While thedeflection yoke 126 implies a magnetic deflection system, it isunderstood that electrostatic deflection could also be used as well as atwo axis mechanical scribing device when a permanent paper record isdesired.

Referring now to FIG. 8 there is seen an alternative embodiment of theinvention which is particularly useful for producing a sequence of tracesegments on a display 130. Two coordinate generators 132A-B providerespectively the X and the Y components on lines l33A-B of each tracesegment for the display 130 in response to signals from a computer 134,these signals being clock, reset, character select and offset signals.Each of the coordinate generators 132A-B is provided with an incrementmemory 136, similar to the increment memory 64A of FIG. 2, which storesinformation with respect to a component of each trace segment so thatthe sequence of trace segments appearing on the display 130 has the formof a character.

The coordinate generators 132A and 1328 each comprise the samecomponents and function in the same manner so that only the coordinategenerator 132A need be described. The coordinate generator 132Acomprises a counter 138, a timing unit 140, an accumulator 142, adigital-to-analog converter 144, a sample and hold circuit 146, a summer148 and a filter system 150. The counter 138 counts pulses provided bythe clock signal of the computer 134 and the value of the count is usedto address the increment memory 136. The maximum count of the counter138 is equal to the maximum number of segments to be utilized inconstructing a character on the display 130. After reaching this maximumcount, the counter 138 is reset to zero by the computer 134. Theincrement memory 136 is also further addressed by the character selectsignal having the form of a binary number appearing on the characterselect line from the computer 134, the character select signaladdressing a subunit of the increment memory 136 which contains theinformation relative to the particular character which is to bedisplayed while the counter 138 provides the address within the subunitto obtain the components of the individual trace segments.

The successive outputs of the increment memory 136 are accumulated bythe accumulator 142 and converted to an analog signal by thedigital-to-analog converter 144 in a manner similar to the operation ofthe accumulator 54A and the digitaI-to-analog converter 56A describedearlier with reference to FIG. 2. The sample and hold circuit 146samples each value of the output voltage of the digital-to-analogconverter 144 whenever this voltage is updated and holds this value online 152 until the next updating of this voltage. The timing unit 140provides timing signals, indicated by the symbols Tl-T4, in response toeach pulse of the clock signal and applies these timing signals T1-T4respectively to the increment memory 136, the accumulator 142, thedigital-to-analog converter 144 and the sample and hold circuit 146 tocoordinate the operations of these components in a manner well known tothe art. For example, the sample and hold circuit 146 is triggered byits timing signal T4 at a fixed delay after the triggering of thedigital-to-analog converter 144 by its timing signal T3 to insure thatall transients within the digital-to-analog converter 144 have died out.Timing signals such as those of the timing unit 140 have not been shownin FIG. 2 since the displaying of the PPI sweeps on the display 28 occurslowly relative to the generation of the trace on the display 130 sothat the effect of transients is not as significant with the system ofFIG. 2; however, for increased precision, timing signals such as thoseof the timing unit 140 may also be employed in the system of FIG. 2. Inthe embodiment of FIG. 8 the increment/decrement signal for theaccumulator 142 as well as the reset signal for the accumulator 142 areprovided by the increment memory 136 so that the accumulator 142 canincrease or decrease the value of its stored number in accordance witheach portion of the character to be generated on the display 130.

The filtering system 150 smooths transitions in the output voltage online 152 of the sample and hold circuit 146 so that the voltage on theline 152 which has the appearance of a sequence of steps correspondingto changes in the contents of the accumulator 142 is transformed to aramp-like voltage on line 154 at the output of the filtering system 150.A preferred form of the filtering system 150 comprises a delay line 156shown as an inductor-capacitor ladder circuit terminated with itscharacteristic impedance via a resistor 158, a well-known summingamplifier comprising an operational amplifier with a feedback element161 of impedance Z, and a set of summing resistors 162 coupledrespectively between taps of the delay line 156 and an input to thesumming amplifier 160. The various resistors 162 have differing valuesof resistance to compensate for attenuation in the delay line 156 sothat, in response to each stepwise change in value of voltage on line152, a succession of small step signals of substantially equal magnitudeappear at the input terminal of the summing amplifier 160. The delay ofthe delay line 156 is approximately equal to the reciprocal of therepetition frequency of the timing signal T4 applied to the sample andhold circuit 146. The impedance Z of the feedback element 161 isselected to provide a bandwidth of the summing amplifier 160 which, incombination with the cutoff frequency of the delay line 156, attenuatesthe high frequency components of the staircase voltage appearing at theinput to the summing amplifier 160, thereby providing the ramp-likevoltage on the line 154. The offset signal of the computer 134 is a stepvoltage and is summed together with the votage on line 154 by the summer148 to provide the X component voltage on line 133A to the X deflectioncircuit, the offset signal serving to position the trace on the display130.

Since both coordinate generators 132A-B are driven by the same signalsof the computer 134, the generation of the X and the Y coordinates ofeach segment of the displayed trace are coordinated so that a charactercan be produced on the display 130. The coordinates are vectoriallycombined in a well-known manner, as by the X and Y deflection plates ofan oscilloscope (not shown), to produce the segments of a trace. Inorder to produce a generally uniform writing speed on the dis play 130and thereby minimize the need for modulating the Z axis for maintaininguniform brightness of the display 130, a lengthy segment of a characteris preferably divided into two or more smaller strokes or segments. Eachsuch segment is obtained by having the increment memory 136 apply aseparate increment for each such segment to the contents of theaccumulator 142. In this way all the portions of a character areproduced during equal intervals of time so that each portion of thecharacter is displayed with equal brightness.

The embodiment of FIG. 8 also utilizes a modulator 164 responsive to theclock, reset and character select signals of the computer 134 formodulating the Z axis of the display 130. The modulator 164 comprises acounter 166 and a memory 168 which function in a manner analogous to thecounter 138 and the memory 136. Thus, for each segment of the trace asis indicated by the address provided by the counter 166, the memory 168provides a high or a low voltage signal for blanking or unblanking the Zaxis. These blanking voltages are coordinated with the ramp voltages ofthe coordinate generators 132A-B by the computer signals and a delayunit 170 which compensates for delays in the coordinate generators132A-B so that the portions of the character corresponding to these rampvoltages are displayed while retrace ramp voltages of the coordinategenerators 132AB are blanked out in a manner well known to the displayart.

A further feature of this embodiment of the invention is the utilizationof a circuit 172 comprising a resistor 174 and a capacitor 176 seriallyconnected between the input of the summing amplifier 160 and the outputof the sample and hold circuit 146 on line 152 for improved linearity ofa trace displayed on the display 130. A well-known charge restoringcircuit 178 is connected across the capacitor 176 for restoring thecharge to a predetermined value after each character or symbol of thetrace on display 130. For example, the charge restoring circuit 178 maycomprise a field effect transistor (FET, not shown) having its sourceand drain terminals connected to the terminals of the capacitor 176while an activating signal voltage provided in a wellknown manner inresponse to a signal of the timing unit 140 is transformer coupledacross the source-gate terminal pair of the FET. The circuit 172provides the improved linearity by applying an additional voltage at theinception of each trace segment to compensate for the delay in responseof the deflection circuits of the display 130 and of the delay line 156to the ramp voltage appearing at the output of the summing amplifier160.

It is understood that the above described embodiments of the inventionare illustrative only in that modifications thereof will occur to thoseskilled in the art. Accordingly, it is desired that this invention isnot to be limited to the embodiments disclosed herein but is to belimited only as defined by the appended claims.

What is claimed is:

1. A coordinate generation system comprising:

means for signaling incremental changes in a desired direction;

means for displaying said direction, said display means having adeflection system utilizing a first coordinate and a second coordinateof said direction;

means coupled to said signaling means for storing data relative toincremental changes in said first and said second coordinates, saidstorage means providing successive incremental coordinate changes inresponse to successive incremental change signals of said signalingmeans; and

means interconnecting said storage means and said display means forcombining successive ones of said incremental coordinate changes toprovide said first and said second coordinates.

2. The system according to claim 1 further comprising meansinterconnecting said storage means with said signaling means foraddressing stored data related to specific ones of said incrementalcoordinate changes.

3. The system according to claim 2 further comprising means coupled tosaid addressing means for controlling said combining means, said controlmeans signaling said combining means to increment and to decrement avalue of one of said coordinates.

4. The system according to claim 3 wherein said combining meanscomprises a digital-to-analog converter and means for selecting apositive or negative output of said digital-to-analog converter.

5. The system according to claim 4 wherein said digitalto-analogconverter includes means responsive to a scaling signal for scaling theoutput signal of said digital-to-analog converter.

6. The system according to claim 5 further comprising a transceiver,said transceiver providing said scaling signal.

7. The system according to claim 6 wherein said transceiver is coupledto said display means, said display means displaying data provided bysaid transceiver.

8. The system according to claim 2 further comprising means responsiveto signals of said storage means for controlling said combining means,said control means signaling said combining means to increment and todecrement the value of one of said coordinates in accordance with anincremental coordinate change provided by said storage means.

9. The system according to claim 8 wherein said combining meanscomprises a digital-to-analog converter and means for selecting apositive or negative output of said digital-to-analog converter.

10. The system according to claim 9 wherein said digital-to-analogconverter includes means responsive to a scaling signal for scaling theoutput of said digitalto-analog converter, said system furthercomprising a transceiver providing said scaling signal, said transceiverbeing coupled to said display means, and said display means displayingdata of said tranceiver.

11. The system according to claim 2 wherein said storage means comprisestwo sections, each of said sections being simultaneously addressed bysaid addressing means, said storage means including means forselectively coupling said combining means to each of said sections ofsaid storage means.

12. The system according to claim 11 wherein said combining meansincludes a digital-to-analog converter and means for selecting apositive or negative output of said digital-to-analog converter.

13. The system according to claim 12 further comprising means coupled tosaid signaling means for controlling said addressing means, saidcombining means, said selection means of said storage means, and saidselection means coupled to said digital-to-analog converter; saidcontrol means signaling said addressing means to increment its addressin a forward direction and in a reverse direction, and said controlmeans signaling said combining means to increment or decrement the valueof a coordinate provided by said combining means.

14. The system according to claim 13 wherein said combining meansincludes means for scaling the value of a coordinate provided by saidcombining means.

15. In combination:

means responsive to an angle of rotation for signaling incrementalchanges in said angle;

means responsive to said incremental changes of said signaling means forgenerating a signal having values related in a presecribed functionalmanner to said incremental angular changes, said generating meanscomprising memory means for storing data relative to incremental valuesof said function for providing said incremental values, means responsive to said incremental angular changes for addressing successiveportions of said memory means, and means for combining the storedfunctional increments of said address portions of said memory means toprovide said signal having said functional relationship; and

means for combining a plurality of said signals having said functionalrelationship for displaying said angle of rotation.

16. The combination according to claim 15 wherein said angle of rotationis provided by a rotating antenna, said combination further comprisingmeans for rotating said antenna, said signaling means being driven bysaid rotating means in synchronism with said antenna.

17. The combination according to claim 16 further comprising transceivermeans coupled to said antenna and to said means for combining saidfunctions, said transceiver providing a scaling signal synchronized witha transmission of radiant energy via said antenna, said combining meansof said function comprising means for scaling said function inaccordance with said scaling signal.

18. The combination according to claim 17 wherein said combining meanscomprises cathode ray tube means for said displaying of said angle ofrotation, said transceiver means transmitting data received by saidantenna to said display means.

19. In combination:

a plurality of means for generating a function, each of said functiongeneration means being responsive to timing signals and scaling signals;

programming means providing said timing siangals and said scalingsignals to said function generation means;

each of said function generation means comprising a memory for storingincremental values of a signal waveform, successive portions of saidmemory being addressed successively in response to said timing signals,each of said function generation means further comprising means forcombining said incremental portions of said signal waveform to producesaid signal waveform, each of said function generation means includingmeans for providing a second signal waveform, each of said signalwaveforms having a magnitude determined by said scaling signals;

means for displaying symbols;

the memory in one of said function generation means providing signalwaveforms representing the instantaneous values of the coordinates of asymbol displayed by said display means, the memory in a second one ofsaid function generation means providing a signal waveform representingthe values of the coordinates of the position of said symbol on saiddisplay means; and

said display means comprising means for combining the signal waveformsfrom each of said function generation means, means for filtering saidcombined signal waveforms to provide deflection signals suitable forproducing said symbol, said display means further comprising meansresponsive to a signal of said programmer means for modulating theintensity of said display.

20. A system generating coordinates of data points suitable forpresentment on a display, the system providing said coordinates inresponse to incremental changes in the position of an object, the systembeing characterized by the comprising of:

means for storing incremental values of signal waveforms representingvariations in the values of said coordinates as a function of saidincremental changes;

means responsive to successive ones of said incremental changes forsuccessively addressing said storage means to extract successive ones ofsaid stored incremental values;

means for combining said extracted values to provide the waveform of acoordinate signal; and

means utilizing said coordinates to display said data at coordinatescorresponding to the position of said object.

21. In combination:

a plurality of generators, each of said generators comprising means forstoring differences between values of data; and means for accumulatingsaid differences to provide said values of data; and

means coupled to each of said generators for displaying data composedfrom said values of data, said displaying means including means forvectorially combining said values of each of said generators.

22. The combination according to claim 21 further comprising meanscoupled to each of said generators for selecting individual ones of saiddifferences of said storage means.

23. The combination according to claim 22 further comprising meanscoupled between said plurality of generators and said display means forfiltering said values of data.

24. The combination according to claim 23 wherein said filtering meanscomprises a tapped delay line, means for combining signals obtained fromthe taps of said delay line and means by-passing said delay line forcompensating for a temporal response lag of said delay line and saiddisplay means.

1. A coordinate generation system comprising: means for signalingincremental changes in a desired direction; means for displaying saiddirection, said display means having a deflection system utilizing afirst coordinate and a second coordinate of said direction; meanscoupled to said signaling means for storing data relative to incrementalchanges in said first and said second coordinates, said storage meansproviding successive incremental coordinate changes in response tosuccessive incremental change signals of said signaling means; and meansinterconnecting said storage means and said display means for combiningsuccessive ones of said incremental coordinate changes to provide saidfirst and said second coordinates.
 2. The system according to claim 1further comprising means interconnecting said storage means with saidsignaling means for addressing stored data related to specific ones ofsaid incremental coordinate changes.
 3. The system according to claim 2further comprising means coupled to said addressing means forcontrolling said combining means, said control means signaling saidcombining means to increment and to decrement a value of one of saidcoordinates.
 4. The system according to claim 3 wherein said combiningmeans comprises a digital-to-analog converter and means for selecting apositive or negative output of said digital-to-analog converter.
 5. Thesystem according to claim 4 wherein said digital-to-analog converterincludes means responsive to a scaling signal for scaling the outputsignal of said digital-to-analog converter.
 6. The system according toclaim 5 further comprising a transceiver, said transceiver providingsaid scaling signal.
 7. The system according to claim 6 wherein saidtransceiver is coupled to said display means, said display meansdisplaying data provided by said transceiver.
 8. The system according toclaim 2 further comprising means responsive to signals of said storagemeans for controlling said combining means, said control means signalingsaid combining means to increment and to decrement the value of one ofsaid coordinates in accordance with an incremental coordinate changeprovided by said storage means.
 9. The system according to claim 8wherein said combining means comprises a digital-to-analog converter andmeans for selecting a positive or negative output of saiddigital-to-analog converter.
 10. The system according to claim 9 whereinsaid digital-to-analog converter includes means responsive to a scalingsignal for scaling the output of said digital-to-analog converter, saidsystem further comprising a transceiver providing said scaling signal,said transceiver being couplEd to said display means, and said displaymeans displaying data of said tranceiver.
 11. The system according toclaim 2 wherein said storage means comprises two sections, each of saidsections being simultaneously addressed by said addressing means, saidstorage means including means for selectively coupling said combiningmeans to each of said sections of said storage means.
 12. The systemaccording to claim 11 wherein said combining means includes adigital-to-analog converter and means for selecting a positive ornegative output of said digital-to-analog converter.
 13. The systemaccording to claim 12 further comprising means coupled to said signalingmeans for controlling said addressing means, said combining means, saidselection means of said storage means, and said selection means coupledto said digital-to-analog converter; said control means signaling saidaddressing means to increment its address in a forward direction and ina reverse direction, and said control means signaling said combiningmeans to increment or decrement the value of a coordinate provided bysaid combining means.
 14. The system according to claim 13 wherein saidcombining means includes means for scaling the value of a coordinateprovided by said combining means.
 15. In combination: means responsiveto an angle of rotation for signaling incremental changes in said angle;means responsive to said incremental changes of said signaling means forgenerating a signal having values related in a presecribed functionalmanner to said incremental angular changes, said generating meanscomprising memory means for storing data relative to incremental valuesof said function for providing said incremental values, means responsiveto said incremental angular changes for addressing successive portionsof said memory means, and means for combining the stored functionalincrements of said address portions of said memory means to provide saidsignal having said functional relationship; and means for combining aplurality of said signals having said functional relationship fordisplaying said angle of rotation.
 16. The combination according toclaim 15 wherein said angle of rotation is provided by a rotatingantenna, said combination further comprising means for rotating saidantenna, said signaling means being driven by said rotating means insynchronism with said antenna.
 17. The combination according to claim 16further comprising transceiver means coupled to said antenna and to saidmeans for combining said functions, said transceiver providing a scalingsignal synchronized with a transmission of radiant energy via saidantenna, said combining means of said function comprising means forscaling said function in accordance with said scaling signal.
 18. Thecombination according to claim 17 wherein said combining means comprisescathode ray tube means for said displaying of said angle of rotation,said transceiver means transmitting data received by said antenna tosaid display means.
 19. In combination: a plurality of means forgenerating a function, each of said function generation means beingresponsive to timing signals and scaling signals; programming meansproviding said timing siangals and said scaling signals to said functiongeneration means; each of said function generation means comprising amemory for storing incremental values of a signal waveform, successiveportions of said memory being addressed successively in response to saidtiming signals, each of said function generation means furthercomprising means for combining said incremental portions of said signalwaveform to produce said signal waveform, each of said functiongeneration means including means for providing a second signal waveform,each of said signal waveforms having a magnitude determined by saidscaling signals; means for displaying symbols; the memory in one of saidfunction generation means providing signal waveforms representing theinstantaneous values of thE coordinates of a symbol displayed by saiddisplay means, the memory in a second one of said function generationmeans providing a signal waveform representing the values of thecoordinates of the position of said symbol on said display means; andsaid display means comprising means for combining the signal waveformsfrom each of said function generation means, means for filtering saidcombined signal waveforms to provide deflection signals suitable forproducing said symbol, said display means further comprising meansresponsive to a signal of said programmer means for modulating theintensity of said display.
 20. A system generating coordinates of datapoints suitable for presentment on a display, the system providing saidcoordinates in response to incremental changes in the position of anobject, the system being characterized by the comprising of: means forstoring incremental values of signal waveforms representing variationsin the values of said coordinates as a function of said incrementalchanges; means responsive to successive ones of said incremental changesfor successively addressing said storage means to extract successiveones of said stored incremental values; means for combining saidextracted values to provide the waveform of a coordinate signal; andmeans utilizing said coordinates to display said data at coordinatescorresponding to the position of said object.
 21. In combination: aplurality of generators, each of said generators comprising means forstoring differences between values of data; and means for accumulatingsaid differences to provide said values of data; and means coupled toeach of said generators for displaying data composed from said values ofdata, said displaying means including means for vectorially combiningsaid values of each of said generators.
 22. The combination according toclaim 21 further comprising means coupled to each of said generators forselecting individual ones of said differences of said storage means. 23.The combination according to claim 22 further comprising means coupledbetween said plurality of generators and said display means forfiltering said values of data.
 24. The combination according to claim 23wherein said filtering means comprises a tapped delay line, means forcombining signals obtained from the taps of said delay line and meansby-passing said delay line for compensating for a temporal response lagof said delay line and said display means.